1. Field
The present invention relates to an optical-switch drive circuit and may be applied to a drive circuit including for a semiconductor optical amplifier (SOA) gate switch that is used in a matrix optical switch unit of an optical packet switching system in an optical communication network.
2. Description of the Related Art
High-speed large-capacity optical communication apparatuses are required for future multimedia networks. As a system for realizing such a high-speed and large-capacity system, research and development has been in progress regarding an optical packet switching system that uses high-speed optical switches functioning in nanoseconds.
An SOA gate switch is a device that can switch in nanoseconds, and is expected to be applied to an optical packet switching system.
FIG. 9A illustrates a general optical packet switching network, FIG. 9B illustrates a configuration of an edge node EN, and FIG. 9C illustrates a configuration of a core node CN. The optical packet switching network includes a plurality of core nodes CNs which are connected to edge nodes ENs via an optical access network ANW. Each node is connected by data channels DC and a control channel CC.
The core node CN, which is illustrated in FIG. 9C, has a matrix optical-switch function for switching optical packet signals. Optical packet data from the data channels DC, after its wavelength is converted by a wavelength converter WC, is provided to a matrix optical switch MSW.
In the control channel CC, routing information of an optical packet signal is relayed as a label signal between nodes via an optical-electrical (electrical-optical) converter CNV. A reservation manager RM analyzes the routing information of the label and controls the matrix optical switch MSW. Hence the route of optical packet data, whose wavelength has been converted by the wavelength converter CNV, is switched by the matrix optical switch MSW, under the control of the reservation manager RM.
FIG. 10 is a diagram illustrating timings of the switching. In the matrix optical switch MSW, route switching is performed at a predetermined offset time, (OT in FIG. 10) after receiving the label signal having the routing information of the control channel CC. The switching time (ST in FIG. 10) of the optical switch is about 10 ns, which is a guard period that prevents an optical packet signal from being affected. In other words, the switching of an optical packet signal needs to be completed during the guard period.
FIG. 11 illustrates an example configuration of the matrix optical switch MSW, which is a distributive optical switch using SOA gate switches.
First, optical packet signals PKT#1, PKT#2, PKT#3, etc, each of which has a specified output destination as illustrated in FIG. 11, are received at input ports Pi#1 to Pi#n. In FIG. 11, packets having the same packet number from different originating ports are identified by diagonal or dotted shading. The input packets received at the input ports Pi#1 to Pi#n, undergo distribution by optical couplers DCLs and then desired optical-packet-signal route switching that is realized by high-speed selection based on on/off states of SOA gate switches GSWs. Output packets from the SOA gate switches GSWs, which are controlled by the reservation manager RM, are merged by optical merging couplers CPLs that perform merging of optical packet signals, and are output from desired ports among the ports Po#1 to Po#n.
For instance, an optical packet signal PKT#n having a destination of the output port Po#n, input at the input port Pi#1, is branched in parallel into n signals by the optical coupler DCL. The optical signals, after 1-to-n branching, are input to the SOA gate switches GSWs provided for respective output ports Po#1 to Po#n. Since the optical packet signal is to be output to the output port Po#n in the case, only the SOA gate switches GSWs provided for the output port Po#n are turned on by the control signal from the reservation manager RM. All the SOA gate switches GSWs provided for other output ports are kept in the off state.
FIG. 12 illustrates an example operation of the SOA gate switch GSW, and FIG. 13 illustrates an example configuration for driving the SOA gate switch GSW. The SOA gate switch GSW is a device that can amplify an optical signal propagating through an optical-signal amplification region ROA by injecting a current into the optical-signal amplification region ROA. The SOA gate switch GSW is used as a gating element for an optical signal, operating by on/off control of its drive current IGSW.
The example illustrated in FIG. 12 corresponds to a state where, for the input optical packet signals PKT#1, PKT#2, and PKT#3, drive circuit control is performed such that the gate is on for the packets PKT#1 and PKT#3, and the gate is off for the packet PKT#2.
For the control, the SOA gate switch GSW is controlled by a control signal CONT from the reservation manager RM via an optical-switch drive circuit 1 as illustrated in FIG. 13.
FIG. 14 illustrates optical gain versus drive current IGSW for the SOA gate switch GSW. The SOA gate switch GSW, a semiconductor optical amplifier, has a characteristic in which its optical gain varies with the drive current IGSW. Referring to FIG. 14, the optical gain becomes approximately 10 dB at a flowing drive current of approximately 300 mA, where the gain is nearly saturated (the on state). As the drive current IGSW decreases, the gain decreases, illustrating a characteristic of attenuation, and becomes approximately −60 dB in the off state.
FIG. 15 illustrates optical gain versus drive voltage VGSW for the SOA gate switch GSW. Although the SOA gate switch GSW is a current driven switch, it can be used as a voltage driven switch by applying a voltage using a voltage source having a current capacity of 300 mA or more. In the example, the optical gain is 10 dB at a voltage of approximately 1.5 V, entering the on state with a drive current of approximately 300 mA as can be seen from FIG. 14. As the drive voltage decreases, the gain decreases, illustrating the characteristic of attenuation, and also becomes approximately −60 dB in the off state.
FIG. 16 illustrates the drive voltage VGSW of the SOA gate switch GSW versus the inter-SOA-gate-switch extinction ratio (on/off ratio).
Each of the optical merging couplers CPLs at the output of the matrix optical switch MSW illustrated in FIG. 11 is provided with the SOA gate switches GSWs in a number equal to the input ports of the matrix optical switch MSW. When a certain SOA gate switch GSW is on, all the rest of the SOA gate switches GSWs are in the off state. However, there is leakage of light even in the off state, causing crosstalk of light in the optical merging coupler CPL.
FIG. 16 illustrates the crosstalk as an extinction ratio characteristic. When an 8-by-8 matrix optical switch is to be configured, approximately 58 dB is required as an extinction ratio characteristic corresponding to on and off states. To obtain the extinction ratio characteristic, the drive voltage VGSW must be set to 0.65 V or less.
FIG. 17 illustrates a drive circuit 1a for an SOA gate switch, according to a typical technology.
Referring to FIG. 17, a parasitic inductance L1 within a connection line between the SOA gate switch GSW and the drive circuit 1a is a parasitic inductance component that is generated when a high frequency signal passes through a substrate pattern of the drive circuit 1a. A parasitic inductance L2 is a parasitic inductance component that is generated when a high frequency signal passes through a transmission line within a module MDL in which the SOA gate switch GSW is housed. A diode D1 connected in parallel with the SOA gate switch GSW is a Schottky diode.
The drive circuit 1a has high-speed operational amplifiers OP1 to OP3. The operational amplifier OP1 has an output current capacity of 300 mA, and has the following performance: a bandwidth of approximately 1 GHz, a slew rate of approximately 5000 V/μs, and a settling time of approximately 2 ns. A power source having a DC voltage VSET1 of 0.825 V is connected to a non-inverting input terminal of the operational amplifier OP1. The voltage VSET1 is amplified to a voltage VSET2 of 1.65 V by the high-speed operational amplifier OP1 that has a gain (1+R2/R1) of two using resistors R1 and R2.
The drain terminal D of a high-speed field effect transistor FET1 is connected to the output terminal of the operational amplifier OP1. The source terminal S of the transistor FET1 is connected to the drain terminal D of a transistor FET2, whose source terminal S is connected to the ground.
A connection node between the transistors FET1 and FET2 is connected to the SOA gate switch GSW via the parasitic inductance L1 of a transmission line of the substrate and the parasitic inductance L2 of a transmission line within the SOA gate switch module MDL. The high-speed Schottky diode D1 is a diode used for suppressing ringing when the SOA gate switch GSW is turned off.
CONT in FIG. 17 denotes a control signal for switching the SOA gate switch GSW on/off. The control signal CONT is supplied via a buffer BUF1 to an inverter INV and a buffer BUF2 (buffer having a delay characteristic equivalent to that of the inverter INV). The operational amplifiers OP2 and OP3 are respectively connected to the buffer BUF2 and the inverter INV. The operational amplifiers OP2 and OP3 are high-speed driving amplifiers used for respectively driving the transistors FET1 and FET2. The operational amplifiers OP2 and OP3 have a performance similar to that of the operational amplifier OP1, i.e., they correspond to the operational amplifier OP1 whose gain is set to “1”.
The control signal CONT, when it is set to a high level “1”, will cause the transistor FET1 to turn on and the transistor FET2 to turn off via the buffer BUF2 and the operational amplifier OP2. Hence the output voltage VSET2 of the operational amplifier OP1 is applied to the SOA gate switch GSW via the transistor FET1 and the parasitic inductances L1 and L2. The transistor FET1, which has an internal resistance of 0.5 Ω, will have a voltage drop of 0.15 V when a current of 300 mA is passed therethrough. Hence, the voltage VOUT of the connection node between the transistors FET1 and FET2, i.e., an input voltage of the SOA gate switch GSW, is set to 1.5V(=1.65V-0.15V).
On the other hand, to turn the SOA gate switch GSW off, the control signal CONT is set to a low level “0”. By the control, the transistor FET1 is turned off, the transistor FET2 is turned on, the input voltage VOUT is set to the ground level, and a current stops flowing in the SOA gate switch GSW, which is the off state.
As a typical technology, for example, Japanese Unexamined Patent Application Publication No. 2002-335038 discusses a light-emitting-device driving apparatus and a light-emitting-device driving system, where light emitting devices in a surface-emitting laser system are driven such that, while each light emitting device is made to be in a forward-biased state, either a bias voltage lower than a lasing threshold voltage or a drive voltage above or equal to the lasing threshold voltage is applied, through appropriately switching, directly to the drive terminal of the light emitting device.
FIG. 18 illustrates operation waveforms that exist during the driving operation of an SOA gate switch of the typical technology illustrated in FIG. 17. Referring to FIG. 18, VOUT is a source voltage waveform of the transistor FET1, VGSW is an anode voltage waveform of the SOA gate switch GSW, and IGSW is a current waveform of the SOA gate switch GSW. In the waveforms illustrated in FIG. 18, ringing at the rising edge of the voltage VOUT appears also in the waveform of the current IGSW of the SOA gate switch GSW. Ringing, also generated in the optical output of the SOA gate switch GSW, will cause an optical surge and, therefore, may cause an optical receiver to deteriorate. This is due to the following reason. Since the operational amplifiers OP1 to OP3 operate in nanoseconds, a resistor component R of the transistor FET1 and parasitic inductances L1 and L2 form an L-R circuit, and its transient phenomenon causes the rising waveform of the voltage VOUT to become less steep.
The ringing, which becomes a noise in a main signal superimposed on light, may cause an error. Furthermore, it takes approximately 15 ns for the ringing of the current IGSW to settle, leading to a slow rise time of the waveform. In addition, assuming an internal resistance of the transistor FET1 to be 0.5 Ω, a power of approximately 45 mW is consumed at 300 mA. Since a large drive current is used, the power consumption within the transistor FET1 will markedly increase as the internal resistance of the transistor FET1 used increases.
The falling edge of the waveform of the current IGSW also has a ringing portion of about 1.5 ns, since charge accumulated in the junction capacitance (approximately 70 pF) is discharged; however, the optical signal is not affected, since the extinction ratio of the SOA gate switch GSW is 58 dB or more when the voltage VGSW becomes lower than 0.65 V.
Note that a rise time is a time from a start point at which the voltage applied to the SOA gate switch GSW is 0.65 V, which satisfies the extinction ratio characteristic, until an end point at which a current flowing in the SOA gate switch GSW reaches 90% of the steady state value of 300 mA, namely approximately 270 mA. A fall time is a time from a start point at which a current flowing in the SOA gate switch GSW decreases to 90% of the steady state value of 300 mA, namely approximately 270 mA, until an end point at which the voltage applied to the SOA gate switch GSW falls to 0.65 V, which satisfies the extinction ratio characteristic.